There continues to be a tremendous increase in demand for more storage space, and higher throughput for the devices that provide the storage. Solid state technology has many performance and technical advantages over traditional spinning disk storage, and solid state drives (SSDs) find increasing use. The capacity of SSDs is approaching the capacities of devices made with traditional spinning disk technologies, and the prices are coming down to a level considered more affordable.
However, capacity is not the only measure of interest with SSDs. Unfortunately, higher capacity SSDs do not currently offer equivalent performance of lower capacity drives. Research indicates that mid-range capacity SSDs provide the best throughput. The SSD storage controller requires that a memory channel to the nonvolatile memory (NVM) devices drive a minimum number of memory devices or dies to keep the command and data buses at maximum activity, and to have the memory dies accessed in parallel. Increasing the number of memory dies on memory channel eventually reduces overall throughput performance when the increased capacitive loading requires a reduction in the clock frequency on the bus between controller and the NVM devices. For a single memory channel, a system designer traditionally has to choose between high bandwidth and low capacity, or low bandwidth and high capacity.
Since the tradeoff is typically thought of with respect to a single channel, a common solution is to add memory channels, and configure them all for higher bandwidth and lower capacity. However, adding more channels increases the die size and package size of the controller as well as the SSD itself. Increased controller size and packaging increases the cost.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.